Prior to installation in machines, manufacturers and assemblers, for instance, often test processor chips (“chips”) to determine their performance metrics. These metrics involve investigating chip performance using functional and non-functional test sequences throughout predetermined windows, e.g., operational, for several variables, including chip voltage, clock speed, power and temperature. Although testing various chips' performance metrics readily allows for sorting these chips into their proper class of machine, testing is also used to identify chip failures, allow higher machine manufacturing productivity, and improve product quality.
LGA generically refers to interconnect technology for connecting a module, i.e., chip, to a board. From a board perspective, the board is said to have an LGA site or socket. From a module perspective, the module is said to have an LGA surface. Regardless of which perspective, the electronic connection between the module having the chip and the board is the same; that is, connection is via a conductive material called an LGA interposer. To make the temporary or permanent connection between the board and module, oftentimes there is a loading mechanism, such as squeezing, wherein the connection results. For testing environments, temporary is likely preferred because connection is for a limited time and purpose, i.e., testing. By comparison, connections in commercially available computers are often permanent.
For testing, chips are often attached to a temporary carrier, e.g., ceramic, and then placed in a device tester for testing. Before discussing testers, a brief discussion of chip testing terminology is helpful. Temporary chip attachment of a single chip is called TCA, and, it follows that the temporary carrier for the TCA is called a TCA carrier. Alternatively, the chip(s) may not be placed on a temporary carrier, but be immediately placed on its final production level carrier. In this case, the module is referred to as single chip module (SCM) or multichip module (MCM), depending on whether one or more chips are placed on the carrier. Upon placing the TCA, SCM or MCM into a tester, this module is understood to be the device under test, i.e., DUT. After testing the TCA, the chip is normally sheared from its TCA carrier, which is normally recycled for use as a carrier for future testing, and the chip(s) are permanently mounted on its final carrier.
Testers, themselves, include one or more chip testing components, which enable determination of chip performance metrics and their ultimate characterization. Previous testers include Early Run-In Functional (“ERIF”) 3 and ERIF-4. The tester controls the applied voltage, the clock frequency, test sequences, power, and temperature. Despite differing architectures, as a whole, testers typically include: 1) a test board that is compatible with the class of DUT; 2) a control computer to control the test sequences; 3) programmable power sources, control hardware to control delivery of test resources, e.g., voltage, current, pneumatics, coolant fluid, etc.; 4) a chiller to deliver coolant fluid to the DUT; 5) network interface and communication hardware/software; and 6) a test nest, which is the portion of the tester that physically accommodates the DUT.
Despite advances in testing chips, problems and inefficiencies remain in the testers and methods used for testing modules as the DUTs. For example, nests are unnecessarily cumbersome, a problem which results in a disproportionately large nest footprint, and, thereby, seizes otherwise useable and valuable test volume; the cumbersome nest architecture also lends itself to unnecessary difficulties in installation and replacement of test sockets. In addition, testers often have external parasitic loads and moments acting on the heatsink and chip surface without having an ability to isolate and/or adjust these loads and moments; as a result, deviations from the chip's true performance metrics, especially those related to temperature, are likely to occur for the DUT. Another problem in the current state of the art is the effect of inattentiveness to controlling condensation on the DUT, wherein, condensation may cause damage to the tester.
In light of the example, above-identified problems, a need, therefore, exists, for improved apparatuses, methods and systems for testing modules as the DUT.